Aiserver Manufacturer
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| Product Introduction | Built on a self-developed general architecture, with core specifications designed around 'high computing power, large memory, low power consumption, and wide compatibility.' |
| Name | Muxi Xiyun C500 64G |
| INT8 | 480 TOPS |
| FP16 | 240 TFLOPS |
| FP32 | 30 TFLOPS |
| VRAM Type | HBM2E (High Bandwidth Memory, with approximately 30% higher bandwidth compared to HBM2, suitable for the high bandwidth demands of large model inference) |
| Chip Fabrication Process | TSMC 7nm FinFET process, paired with 2.5D CoWoS advanced packaging (ensuring core heat dissipation and signal stability) |
| DirectX Support | Compatible with DirectX 12 (including 12_1 features), suitable for mainstream graphics rendering and video processing scenarios |
| Video Memory Frequency | Effective frequency 4000MHz (native high-frequency characteristics of HBM2E, achieving low-latency data transfer with 800GB/s bandwidth) |
| Memory Bus Width | 4096-bit (HBM2E standard bus width design, providing sufficient data channels for 32GB VRAM to avoid bandwidth bottlenecks) |
| Video Memory Speed | 0.5 ns (based on the physical characteristics of HBM2E memory chips, corresponding to an equivalent frequency of 4000 MHz, with latency better than GDDR6) |
| Output Interface | No traditional video output interfaces (DP/HDMI/VGA), focused on data center inference/computing scenarios |
| Output Interface Type | The core interface is PCIe Gen4.0 x16 (bidirectional bandwidth 64GB/s), supporting x86/ARM host interconnection. |
| Form Factor | FHFL dual-slot |
| Weight | 1064g |
